The Post-Silicon Era: What Actually Comes After Moore's Law

When Gordon Moore wrote his 1965 paper for Electronics magazine, he was not describing a law of nature. He was doing accounting. He had four data points, a chart, and a commercial argument: the cheapest cost per component on an integrated circuit was falling, and the number of components at that minimum was roughly doubling each year. He predicted the trend would hold for a decade. It held, in various revised forms, for roughly five.

That distinction — accounting rather than physics — matters enormously for anyone trying to reason about what happens next. Moore's Law never said transistors would keep shrinking. It said the economically optimal number of them per chip would keep rising. Once you internalise that framing, the current moment stops looking like the end of progress and starts looking like a change in where progress is purchased.

The scaling that actually ended

The genuinely load-bearing trend was not Moore's observation but Dennard scaling, described by Robert Dennard and colleagues at IBM in 1974. Dennard's insight was that if you shrink a transistor's dimensions by some factor and shrink its operating voltage by the same factor, the power density stays constant. Smaller transistors switch faster, use less energy per switch, and you can pack more of them into the same thermal budget. For three decades this was the engine of the industry: each new process node delivered more transistors and faster clocks and comparable power.

Dennard scaling broke around 2005, and it broke for a mundane reason. Voltage stopped scaling. Below roughly one volt, the threshold voltage of a transistor cannot be reduced proportionally without leakage current — current that flows when the device is nominally off — rising to dominate the power budget. Static leakage is heat you pay for continuously, in exchange for nothing.

The consequence is visible in any historical clock-speed chart. Consumer processors crossed 3 GHz in 2002 and, twenty-four years later, high-end desktop parts boost to roughly 5.5 to 6 GHz. That is not two decades of stagnation in computing; it is two decades of stagnation in one specific variable. Meanwhile, transistor counts on flagship processors moved from tens of millions to tens of billions, and the industry pivoted from making one core faster to making many cores, then to making many kinds of cores.

The end of frequency scaling did not slow computing down. It changed the currency: performance now costs architecture and software effort rather than a process shrink you could get by waiting.

What "3 nanometres" does and does not mean

A persistent source of public confusion is the process node name. When a foundry announces a 3 nm process, no physical feature on the chip measures three nanometres. A silicon atom's lattice spacing is about 0.54 nm; a functioning gate three nanometres wide would be a handful of atoms across, and no manufacturer claims that. Node names became marketing labels in the early 2010s, decoupled from any single measured dimension.

What has continued to advance is a bundle of related metrics that engineers care about more than the label: transistor density per square millimetre, switching energy, and the ratio of performance to watt at a given frequency. Density gains have continued, though at a slower cadence and at sharply rising cost. Extreme ultraviolet lithography, which uses 13.5 nm light generated by vaporising tin droplets with a laser, made continued patterning possible — and pushed the price of a single leading-edge exposure tool past 150 million dollars, with high-numerical-aperture systems considerably more.

Structurally, the transistor has been redesigned twice in fifteen years to keep leakage under control. The planar transistor gave way to the FinFET, which wraps the gate around three sides of a raised silicon fin to gain electrostatic control over the channel. FinFETs are now giving way to gate-all-around nanosheet transistors, where the gate fully surrounds a stack of thin horizontal channels. Each redesign bought roughly one more generation of usable scaling by improving how firmly the gate can shut the channel off.

Where the last decade of performance actually came from

If you audit the sources of real-world speedup since about 2015, transistor shrink is a minority contributor. Four other levers did most of the work.

Specialisation. A general-purpose core spends most of its transistor budget and most of its energy on flexibility: branch prediction, out-of-order scheduling, register renaming, cache coherence. A fixed-function block that does one thing — video decode, matrix multiplication, cryptographic hashing, image signal processing — can skip nearly all of that overhead. Domain-specific accelerators routinely deliver one to three orders of magnitude better energy efficiency per operation than a general core running the same workload. This is why a modern phone system-on-chip is mostly not CPU: it is a collection of specialised engines sharing memory.

Memory hierarchy. For most of computing's history, arithmetic was expensive and moving data was cheap. That inverted. Reading a value from off-chip DRAM costs on the order of a hundred times more energy than performing a floating-point multiply on data already in a register. Consequently, architects now spend enormous transistor budgets on caches, scratchpads, and prefetchers, and the highest-value optimisation in performance engineering is usually improving data locality rather than reducing instruction count.

Packaging. If you cannot make one large die cheaply — and yield falls sharply with area, because a single fatal defect kills the whole die — you can make several small dies and connect them densely. Chiplet architectures do exactly this, joining separately manufactured tiles through silicon interposers or organic substrates. High-bandwidth memory takes the same idea vertically, stacking DRAM layers connected by through-silicon vias and placing the stack millimetres from the compute die. Packaging is now a first-class scaling axis rather than an afterthought, and much of the recent gain in accelerator throughput is memory-bandwidth gain, not arithmetic gain.

Numerical precision. Deep learning turned out to tolerate remarkably coarse arithmetic. Training moved from 32-bit floats to 16-bit formats, then to 8-bit, and inference now routinely runs at 8-bit integer or 4-bit quantised precision. Halving the bit width roughly halves the memory traffic and lets you pack more arithmetic units into the same area. A substantial share of headline AI-accelerator speedups reflect this reduction in precision rather than any improvement in silicon.

The candidate successors, honestly assessed

Beyond conventional silicon CMOS, several device technologies are genuinely promising in laboratories. Each faces the same brutal asymmetry: the incumbent has sixty years of accumulated manufacturing knowledge, tooling, design software, and yield engineering behind it.

Carbon nanotube transistors. Nanotubes conduct electrons ballistically over short distances and are intrinsically thin, which gives excellent gate control. Research groups have demonstrated working microprocessors built from thousands of nanotube transistors. The difficulty is placement and purity: nanotubes grow with mixed chirality, meaning some are metallic rather than semiconducting, and a metallic tube in the wrong place is a permanent short. Making billions of devices with defect rates measured in parts per billion is a different problem from making thousands.

Spintronics and magnetic logic. Instead of moving charge, encode state in electron spin or magnetic domain orientation. Spin-transfer-torque magnetic memory is already in commercial production as an embedded non-volatile memory, which is a real achievement. Using magnetic state for logic rather than storage remains slower than CMOS switching, so the near-term value is in memory that retains state without power — attractive for edge devices that spend most of their time idle.

Silicon photonics. Light does not suffer resistive loss, and optical links can carry enormous bandwidth over distance. Photonics is already displacing copper for rack-scale and increasingly for package-scale interconnect, and co-packaged optics is arriving in commercial switches. Optical computing is harder: photons do not interact with each other easily, which is exactly what you need for a transistor-like nonlinearity, and optical components are large compared with transistors. The credible role for photonics is communication, not general logic.

Superconducting logic. Josephson-junction circuits switch with extraordinarily low energy per operation and can run at tens of gigahertz. The catch is the refrigerator. Cooling to a few kelvin costs kilowatts of plant per watt of cooling at low temperature, which restricts the technology to settings where the workload is enormous and centralised — or to quantum computing control, where cryogenics are required anyway.

Quantum computing. Worth stating plainly, because the framing is often wrong in public discussion: a quantum computer is not a faster classical computer. It offers asymptotic advantage on a narrow class of problems with exploitable structure — factoring, discrete logarithms, simulating quantum systems, certain sampling and optimisation problems. It will not speed up a spreadsheet, a web server, or most machine-learning training. Error rates remain the central obstacle, and fault-tolerant machines require large numbers of physical qubits per logical qubit. Recent demonstrations that logical error rates fall as the error-correcting code grows are genuinely important results, because they show the scaling direction is favourable, but the engineering distance to broadly useful machines remains substantial.

Why efficiency became the binding constraint

There is a deeper reason to expect architecture and software to matter more than devices for the next decade: the limit is increasingly thermal and electrical rather than geometric.

A dense accelerator rack can draw more than a hundred kilowatts, which exceeds what air cooling handles comfortably and pushes operators toward direct-to-chip liquid cooling. At data-centre scale, the constraint becomes grid interconnection — the multi-year queue to connect new load to transmission infrastructure. In several regions, the practical ceiling on new compute capacity is now the substation, not the fab.

That reframes the engineering objective. When power is the scarce input, the metric that matters is useful work per joule. Improvements to that metric come from removing waste: eliminating unnecessary data movement, using the cheapest adequate numerical precision, keeping specialised units busy, scheduling work where energy is abundant. None of these require a new transistor.

What to watch, and what to discount

If you want to track this transition without being swept along by announcements, a few indicators carry more signal than others.

• Energy per operation at fixed accuracy, rather than peak theoretical throughput. Peak numbers assume perfect utilisation, which real workloads never achieve.
• Achieved memory bandwidth relative to arithmetic capability. Most modern accelerators are bandwidth-bound on real workloads, so bandwidth growth predicts delivered performance better than arithmetic growth.
• Packaging and interconnect roadmaps. Advances in interposers, hybrid bonding, and co-packaged optics reliably translate into product-level gains within a generation or two.
• Defect density and yield disclosures for novel devices. A laboratory demonstration of one working device says little; a credible path to parts-per-billion defect rates says a great deal.

Conversely, discount node-name announcements as performance claims, treat single-benchmark records with suspicion, and be wary of any comparison that changes numerical precision between the two systems being compared.

The realistic shape of the next decade

The most probable outcome is not a replacement of silicon but a thickening of the stack around it. Silicon CMOS continues at a slower, more expensive cadence for the logic layer. Around it, packaging integrates heterogeneous tiles built on different processes. Memory moves physically closer and, in some designs, partly into the compute path. Photonics handles communication beyond a few centimetres. Specialised engines absorb whatever workloads are large and stable enough to justify fixed silicon. Novel devices appear first in niches where their single advantage — non-volatility, cryogenic operation, extreme density — outweighs their manufacturing immaturity.

This is a less dramatic story than "the end of Moore's Law", and a more demanding one. The free lunch of waiting for a faster chip is over; the remaining gains have to be earned by people who understand where the energy in a computation actually goes. For engineers, that is arguably a more interesting era than the one it replaced. The performance is still there. It has simply moved from the fab to the architecture, the compiler, and the code.